Performance Analysis of FPGA Based MAC Unit using DBTNS Multiplier & TRNS Adder for Signal Processing Algorithm

  • Aniruddha Ghosh ECE Department, Calcutta Institute Of Technology, Uluberia, Howrah, W.B, India
  • Amitabha Sinha Birbhum Institute of Engineering & Technology, Suri, Birbhum, W.B, India;
Keywords: Ternary Logic Value (TVL), Trit, Ternary Resdue Number Systems (TRNS), Double Base Ternary Number System (DBTNS), DBTNS Multiplier, TRNS Adder, Multiply-Accumulate Unit (MAC), FPGA, DSP Algorithms


Digital signal processing (DSP) algorithms are actually nothing but sum of product. So, they are computationally intensive. All the mathematical tasks related to DSP algorithm are based on multiplication and addition. So, the implementations of DSP algorithms-based applications extensively require multiplier and adder. Due to extensive use of multiplication and addition operation, speed up cannot be achieved. Designing the high-performance adder and multiplier are primary objective for implementing high performance signal processing applications. This hindrance can be removed by Multiply-Accumulate Unit (MAC). The special feature of a MAC unit is its ability to perform single cycle multiplication and addition operation.The performance of MAC Unit can be improved by using non-binary number system. Ternary value logic (TVL) has the ability to offer several advantages over conventional binary number system like reduce chip area, reduce overall delay. TVL can switch between three levels, such levels denoted by 0, 1, 2. As Residue Number Systems (RNS) can perform "carry free" arithmetic operations, high performance adder can be implemented using RNS in TVL domain (TRNS).  Partial product free multiplication can be implemented by using Double Base Number System in TVL domain (DBTNS). Double Base Ternary Number System (DBTNS) multiplier can perform better than conventional TVL multiplier. A MAC unit is used to perform the multiplication and accumulator operations together to avoid unnecessary overhead on the processor in terms of processing time and the on-chip memory requirements. Keeping in view of these issues, a new architecture is proposed for implementing high performance MAC unit for DSP applications. In this paper, a new approach of designing MAC unit is instigated using DBTNS multiplier and TRNS adder.  A major bottleneck of implementing this architecture is the complexity involved in converting TVL to DBTNS in initial stage and converting TRNS to TVL in final stage. The performance of Ternary Residue Number Systems (TRNS) system depends on selection of moduli because selection of moduli is not properly maintained then it will affect system speed, dynamic range and hardware complexity. Proposed MAC unit is mapped on field programmable gate array (FPGA) for analysis its performance.


(1) Chung-Yu-Wu., "Design& application of pipelined dynamic CMOS ternary logic & simple ternary differential logic” IEEE journal on solid

state circuits, 28: 895-906, 1993.

(2) S.L. Hurst, "Multiple-valued logic--its status and its future," IEEE Transactions on Computers, vol. C-33, no. 12, pp. 1160-1179, December 1984.

(3) Reto Zimmermann “Lecture notes on Computer Arithmetic: Principles,Architectures and VLSI Design,” Integrated System Laboratory, Swiss Federal Institute of Technology (ETH) Zurich, Mar,16, 1999. URL

(4) Sanjit K.Mitra “Digital Signal Processing”,A Wiley-Inter science Publication,1999.

(5) Kai Hwang (Purdue University ) and Faye A. Briggs ( Rice University ), “COMPUTER ARCHITECURE AND PARALLEL PROCESSING”, International Edition 1985.

(6) J. P. Hayes, “Computer Organization”, (3rd edition), McGraw-Hill, 1998.

(7) R.Mariani, F.Pessolano & R.Saletti ‘ A new CMOS ternary logic design for low power low voltage circuit’ Tutorial University of Pisa, Italy.

(8) Radanovic M. Syrzycki., "Current-mode CMOS adders using multiple-valued logic", Canadian Conference on Electrical and Computer Engineering, 190-193, 1996.

(9) Gonzalez F, Mazumder P., "Multiple-valued signed digit adder using negative differential resistance devices." IEEE Trans. on Computers. 47: 947 - 959, 1998.

(10) Wei Wang, M.N.S. Swamy, and M.O. Ahmad, "Modulii Selection in RNS for Efficient VLSI Implementation", IEEE Press, New York, pages. IV-512 ~ 515, May, 2003.

(11) Chao-Lin Chiang and Lennart Johnsson, "Residue Arithmatic and VLSI" Presented at 1983 IEEE Internal Conference on Computer Design: VLSI in Computers (ICCCD'83), New York, Oct. 31 - Nov 3, 1983.

(12) Eep Setiaarif, Pepe Siy, "A New Modulii Set Selection Technique To Improve Sign Detection And Number Comparison In Residue Number System (RNS)", NAFIPS 2005 - 2005 Annual Meeting of the North American Fuzzy Information Processing Society, IEEE Press, New York, pages 766 ~ 768, 2005.

(13) Abdallah, M. and A. Skavantzos, “On multi moduli residue number systems with moduli of forms {ra, rb-1,rc+1}”, IEEE Trans. Circuits Syst. I: Regular Paper, Vol.52, pages 1253-1266, 2005.

(14) M. Hosseinzadeh and K. Navi, "A New Moduli Set for Residue Number System in Ternary Valued Logic", Journal of Applied Sciences, Vol. 7(23), pages 3729-3735, 2007.

(15) Mandyam S. and Stouraitis T. “Efficient Analog to Residue Conversion Schemes”. IEEE International Symposium on Circuits and Systems. New Orleans, USA, pages 2885-2888, May 1990.

(16) V. S. Dimitrov, G. A. Jullien, W. C. Miller, Theory and Applications of the Double-Base Number System. IEEE Trans. Computers, Vol. 48, 10, pp.1098-1106, 1999.

(17) Satrughna Singha, Aniruddha Ghosh and Amitabha Sinha, “A New Architecture for FPGA based Implementation of Conversion of Binary to Double Base Number System (DBNS) Using Parallel Search Technique”, ACM SIGARCH Computer Architecture News, Volume 39, Issue 5, pp. 12-18, ACM New York, USA, December 2011. DOI:10.1145/2093339.2093343.

(18) R. Tessier and W. Burleson, Reconfigurable computing for digital signal processing: A survey, Journal of VLSI Signal Processing, Vol 28, no.7-27, pp 7-27, 2001.

(19) Yoeli M, Rosenfeld G., "Logical Design of ternary switching circuits." IEEE Trans Computer., 14: 19-29, 1965.

(20) Parhami, B., “Computer Arithmetic: Algorithms and Hardware Designs”, 1st Edn., Oxford University Press, Oxford, UK., 2001, ISBN: 0-19-512583-5.

(21) K.C.Smith ‘Multiple Valued Logic: A tutorial & application’IEEE Tran. Computer Vol.21 p.p.17-21April 1988.

(22) Satrughna Singha and Amitabha Sinha, “Survey of Various Number Systems and Their Applications”, International Journal of Computer Science and Communication, Volume-1, Number-1, pp. 73-76, Serials Publications, Kurukshetra University, Haryana, India, January

(23) V. S. Dimitrov, S. Sadeghi-Emamchaie, G. A. Jullien, W. C. Miller, A Near Canonic Double-Based Number System (DBNS) with Applications in Digital Signal Processing. Proceedings SPIE Conference on Advanced Signal Processing, August, 1996.

(24) Aniruddha Ghosh and Amitabha Sinha, "FPGA Implementation of MAC Unit for Double Base Ternary Number System (DBTNS) and its Performance Analysis", International Journal of Computer Applications, Volume 181, Issue 14, pp. 9-22, September 2018, Foundation of Computer Science (FCS), NY, USA, DOI:10.5120/ijca2018917785.

(25) R. Muscedere, V. S. Dimitrov, G. A. Jullien, W. C. Miller, M. Ahmadi, On Efficient Techniques for Difficult Operations in One and Two-digit DBNS Index Calculus. Proceedings 34th Asilomar Conference on Signals, Systems and Computers, November, 2000.

(26) Fred J. Taylor, "Residue Arithmetic: A Tutorial with Examples", IEEE Trans. on Computer, pp. 50~62, May 1984.

(27) Conway, R. and J. Nelson, “Improved RNS FIR filter architectures. IEEE Trans”, Circuits Syst. II: Express Briefs, Vol. 51, pages 26-28, 2004.

(28) Aniruddha Ghosh, Satrughna Singha and Amitabha Sinha, “A New Architecture for FPGA Implementation of A MAC Unit for Digital Signal Processors using Mixed Number System”, ACM SIGARCH Computer Architecture News, Volume 40, Issue 2, pp. 33-38, ACM New York, USA, May 2012. DOI:10.1145/2234336.2234342.

(29) A. Sinha, P. Sinha, K. Newton, K. Mukherjee, Multi based number systems for performance enhancement of Digital Signal Processors. Filed for U.S. patent. (U.S. Pat. Appl. No. 11/488,138 ) ,published in U.S. Patent documents serial no.488138 ,U.S. Class at publication 708/620, int'l class : G06F 7/52 20060101 G06F007/52, 2006.

(30) J. Eskritt, R. Muscedere, G. A. Jullien, V. S. Dimitrov, W. C. Miller, A 2-Digit DBNS Filter Architecture. Proceedings SiPS Workshop (Lafayette, L A), October, 2000.

(31) G. A Jullien, V. S. Dimitrov, B. Li, W. C Miller, A. Lee, M. Ahmadi, A Hybrid DBNS Processor for DSP Computation. Proceedings International Symposium on Circuits and Systems, 1999.

(32) Nevio Benvenuto, Lewis E. Franks, and F. S. Hill, Jr. “Realization of Finite Impulse Response Filters Using Coefficients +1, 0 and -1” IEEE Transactions on Communications, vol. COMM-33, no. 10, October 1985.

(33) Dhande P, Ingole VT., "Design of clocked ternary S-R and D flip-flop based on simple ternary gates.", International journal on software engineering and knowledge engineering, 15: 411417, 2005.

(34) Gonzalez F, Mazumder P., "Multiple-valued signed digit adder using negative differential resistance devices." IEEE Trans. on Computers. 47: 947 - 959, 1998.

(35) Radanovic M. Syrzycki., "Current-mode CMOS adders using multiple-valued logic", Canadian Conference on Electrical and Computer Engineering, 190-193, 1996.

(36) Alireza Kaviani and Stephen Brown,"HYBRID FPGA ARCHITECTURE", FPGA.96, Monterey, CA, Feb.1996, pp. 1-7.

(37) C.Rozon ‘On the use of VHDL as a Multivalued Logic Simulator’ Proc. ISMVL 1996,p.p.110-115.

(38) B. G. Lee, A new Algorithm to compute the discrete cosine transforms. IEEE Trans on Acoustics, speech and signal Processing, vol. ASSP-32, pp.1243- 1245, December, 1984.

(39) Ping Wah Wong, “Fully Sigma-Delta Modulation Encoded FIR Filters” IEEE Transactions on Signal Processing, vol. 40, no. 6, pp. 1605-1610, June 1992.