Study of Miniaturization of a Silicon Vapor Chamber for Compact 3D Microelectronics, via a Hybrid Analytical and Finite Element Method

  • Yue MA INL-INSA Lyon, Université de Lyon, 7 avenue Jean Capelle 69621 Villeurbanne, France
  • M. R. S. Shirazy UMI-LN2, Université de Sherbrooke, 2500, boul. de l'Université, Sherbrooke (Québec), Canada, J1K 2R1
  • Q. Struss INL/INSA Lyon, Université de Lyon, 7 avenue Jean Capelle 69621 Villeurbanne, France
  • P. Coudrain STMicroelectronics, 850 rue Jean Monnet 38926 Crolles, France
  • J.P. Colonna CEA-LETI, MINATEC Campus F-38054 Grenoble, France
  • A. Souifi INL/INSA Lyon, Université de Lyon, 7 avenue Jean Capelle 69621 Villeurbanne, France
  • L. G. Fréchette UMI-LN2, Université de Sherbrooke, 2500, boul. de l'Université, Sherbrooke (Québec), Canada, J1K 2R1
  • C. Gontrand INL/INSA Lyon, Université de Lyon, 7 avenue Jean Capelle 69621 Villeurbanne, France

Abstract

The interest in silicon vapor chambers (SVCs) has increased in the recent years as they have been identified as efficient cooling systems for microelectronics. They present the advantage of higher thermal conductivity and smaller form factor compared to conventional heat spreaders. This work aims to investigate the potential miniaturization of these devices, preliminary to integration on the backside of mobile device chips, located as close as possible to hotspots. While detailed numerical models of vapor chamber operation are developed, an easy modeling with low computational cost is needed for an effective parametric study.  Based on the study of the operating limits, this paper shows the thinning potential of a water filled micropillar for a device operating below 10 W and identify the corresponding vapour core height, and wick thickness.

References

(1) D. Milojevic, H. Oprins, J. Ryckaert, P. Marchal, and G. Van Der Plas, “DRAM-on-logic stack - Calibrated thermal and mechanical models integrated into PathFinding flow,” Proc. Cust. Integr. Circuits Conf., pp. 5–8, 2011.

(2) C. Torregiani, H. Oprins, B. Vandevelde, E. Beyne, and I. De Wolf, “Compact thermal modeling of hot spots in advanced 3D-stacked ICs,” Proc. Electron. Packag. Technol. Conf. EPTC, no. 1, pp. 131–136, 2009.

(3) L. Lin, R. Ponnappan, and J. Leland, “High performance miniature heat pipe,” Int. J. Heat Mass Transf., vol. 45, no. 15, pp. 3131–3142, 2002.

(4) W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. R. Stan, “HotSpot: A compact thermal modeling methodology for early-stage VLSI design,” IEEE Trans. Very Large Scale Integr. Syst., vol. 14, no. 5, pp. 501–513, 2006.

(5) W. S. Zhao, J. Zheng, S. Chen, X. Wang, and G. Wang, “Transient Analysis of Through-Silicon Vias in Floating Silicon Substrate,” IEEE Trans. Electromagn. Compat., vol. 59, no. 1, pp. 207–216, 2017.

(6) U. Vadakkan, S. V. Garimella, and J. Y. Murthy, “Transport in Flat Heat Pipes at High Heat Fluxes From Multiple Discrete Sources,” J. Heat Transfer, vol. 126, no. 3, p. 347, 2004.

(7) Y. Luo, B. Yu, X. Wang, and C. Li, “A novel flat micro heat pipe with a patterned glass cover,” IEEE Trans. Components, Packag. Manuf. Technol., vol. 6, no. 7, pp. 1053–1057, 2016.

(8) J. P. Longtin, B. Badran, and F. M. Gerner, “A One-Dimensional Model of a Micro Heat Pipe During Steady- State Operation,” vol. 1, no. AUGUST 1994, 2014.

(9) S. Lips and F. Lefèvre, “A general analytical model for the design of conventional heat pipes,” Int. J. Heat Mass Transf., vol. 72, pp. 288–298, 2014.

(10) L. Lin, R. Ponnappan, and J. Leland, “High performance miniature heat pipe,” Int. J. Heat Mass Transf., vol. 45, no. 15, pp. 3131–3142, 2002.

(11) H. Li, Y. Tang, Y. Jin, B. Li, and T. Zou, “Experimental Analysis and FEM Simulation of Antigravity Loop-Shaped Heat Pipe for Radio Remote Unit,” pp. 1–9, 2017.

(12) R. Hopkins, A. Faghri, and D. Khrustalev, “Flat Miniature Heat Pipes With Micro Capillary Grooves,” J. Heat Transfer, vol. 121, no. 1, pp. 102–109, 1999.

(13) Y. Ma. and C. Gontrand, “Power, Thermal, Noise and Signal Integrity Issues on substrate/Interconnects entanglement” CRC press, 2018.

(14) M. Aghvami and A. Faghri, “Analysis of flat heat pipes with various heating and cooling configurations,” Appl. Therm. Eng., vol. 31, no. 14–15, pp. 2645–2655, 2011.

(15) Z. J. Zuo and A. Faghri, “A network thermodynamic analysis of the heat pipe,” Int. J. Heat Mass Transf., vol. 41, no. 11, pp. 1473–1484, 1998.

(16) U. Vadakkan, J. Y. Murthy, and S. V Garimella, “Transient Analysis of Flat Heat Pipes,” pp. 1–11, 2017.

(17) G. Patankar, J. A. Weibel, and S. V Garimella, “A Time-Stepping Analytical Model for 3D Transient Vapor Chamber Transport,” 2017.

(18) R. S. Prasher, “A Simplified Conduction Based Modeling Scheme for Design Sensitivity Study of Thermal Solution Utilizing Heat Pipe and Vapor Chamber
Technology,” J. Electron. Packag., vol. 125, no. 3, p. 378, 2003.

(19) C. Byon, K. Choo, and S. J. Kim, “Experimental and analytical study on chip hot spot temperature,” Int. J. Heat Mass Transf., vol. 54, no. 9–10, pp. 2066–2072, 2011.

(20) L-M. Collin V. Fiori P. Coudrain S. L. Lhostis S. Chéramy J-P Colonna B. Mathieu A. Souifi, L. G. Fréchette

(21) "Microchannel design study for 3D microelectronics cooling using a hybrid analytical and finite element method ", Proceedings of the ASME 2015, 13th International Conference on Nanochannels, Microchannels, and Minichannels, July 6-9, 2015, San Francisco, California, US.

(22) Y. Yashwanth, J. A. Weibel, and S. V Garimella, “Performance-Governing Transport Mechanisms for Heat Pipes at Ultra-thin Form Factors Performance-Governing Transport Mechanisms for Heat Pipes at Ultra-Thin Form Factors,” vol. 5, no. 11, pp. 1618–1627, 2015.

(23) R. Prieto et al., “Thermal measurements on flip-chipped system-on-chip packages with heat spreader integration,” SEMI-THERM, pp. 221–227, 2015.

(24) F. de Crécy, “A simple and approximate analytical model for the estimation of the thermal resistances in 3D stacks of integrated circuits,” Int. Work. Therm. Investig. ICs Syst., no. September, pp. 1–6, 2012.

(25) Hull R.;, Properties of Crystalline Silicon. London - United Kingdom, 1999.
Published
2019-12-30
How to Cite
MA, Y., Shirazy, M. R. S., Struss, Q., Coudrain, P., Colonna, J., Souifi, A., Fréchette, L. G., & Gontrand, C. (2019). Study of Miniaturization of a Silicon Vapor Chamber for Compact 3D Microelectronics, via a Hybrid Analytical and Finite Element Method. Transactions on Networks and Communications, 7(6), 1-16. https://doi.org/10.14738/tnc.76.7569