An Improved Error Control Model in Packet Switched Wide Area Networks
Error is an important problem in communication that occurs in shared networks when a packet fails to arrive at the destination or it arrives at the destination but some of the bits are in error or have been altered. In typical packet switched wide area networks, this can occur quite easily when output links are slower than inputs and multiple traffic sources competing for same output link at the same time. Typical for packet switched WAN, the packet transmit input/output buffer and queue of the network devices in their way towards the destination. Moreover, these networks are characterized by the fact that packets often arrive in “burst”. The buffers in the network devices are intended to assimilate these traffic hosts until they can be processed. Nevertheless, the available buffers in the network nodes may fill up rapidly if the network traffic is too high which in turn may lead to discarded packets. The situation cannot be avoided by increasing the size of the buffers, since unreasonable buffer size will lead to excessive end-to-end (e2e) delay. A typical scenario for congestion occurs where multiple incoming link feed into single outgoing link (e.g several Local Area Networks connected to Wide Area Networks). The routers of the networks are highly susceptible for traffic congestion because they are too small for the amount of traffic required to handle.
This paper presented general concepts of Error Control and its mechanisms and its application to packet switched wide area networks An improved model was proposed with reduced error while transmitting packets from one channel to the other.
Simulating the model for reducing error control in packet switched wide area networks increased the number of messages, reduced response time used in transmitting and receiving packets, reduced network utilization.
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