TNC Free Running VCO based on an Unstable Transistor Circuit System Stability Optimization under Delayed Electromagnetic Interferences and Parasitic Effects and Engineering Applications

In this article, Very Crucial subject discussed in free running VCO based on an unstable transistor circuit system stability optimization under delayed electromagnetic interferences and parasitic effects. Additionally we discuss Free running VCO integrated circuit applications (PLLs, DLL, clock generation, etc.). There are many techniques to generate a Wideband Frequency Modulation (WBFM) signal: analog based, digitally based and hybrid based techniques. The VCO is a very low cost method of generating WBFM signals, such as chirp signals. The VCO has some important properties that are common to all frequency sources. These properties are frequency range, settling time, post-tuning drift, sensitivity and Maximum Sensitivity Ratio (MSR), frequency total accuracy, frequency modulation span, and modulation frequency bandwidth. The VCO frequency of oscillation depends on the resonance frequency set by its equivalent capacitance and inductance. By applying variable bias voltage to a Varactor diode, the capacitance is changed and the oscillation frequency is changed accordingly. The first delay line in our circuit ( τ 1 ) represents the electromagnetic interference in the Varactor diode (D 1 ). We neglect the voltage on the first delay line (V τ 1 →ε) and the delay is on the current which flows through Varactor diode. The second and third delay lines ( τ 2 and τ 3 ) represent the circuit microstrip line's parasitic effects before and after the matching circuit. We neglect the voltages on the second and third delay lines (V τ k →ε ; k=2, 3) and the delays are only on the current which flow through the microstrip lines. The free running VCO circuit can represent as delayed differential equations which, depending on variable parameters and delays. There is a practical guideline which combines graphical information with analytical work to effectively study the local stability of models involving delay dependent parameters. The stability of a given steady state is determined by the graphs of s ome function of τ 1 , τ 2 , τ 3 . frequency, compared this to a reference signal, and then tweaked the free running VCO voltage to weak its output frequency. The PLL and VCO have been two separate chips – a discrete solution. The free running VCO creates the actual output signal; the PLL monitors the output signals and tunes the free running VCO to lock it relative to a known reference signal. There are a number of strengths to the discrete solution: Each discrete chip can be designed to give its best performance, the typical distance between the PLL and the free running VCO reduces cross-coupling effects and minimizes unwanted spurious signals on the output. In case that one chip in the loop is damaged, fewer components need to be replaced.


Introduction
In this article, Very Critical and useful subject is discussed: free running VCO based on an unstable transistor circuit system stability optimization under delayed electromagnetic interferences and parasitic A voltage-controlled oscillator (VCO) is an electronic oscillator whose oscillation frequency is controlled by the voltage input. The applied input voltage determines the instantaneous oscillation frequency. Our free running VCO is a device based on an unstable transistor circuit. The frequency of oscillation depends on the resonance frequency set by its equivalent capacitance and inductance. By applying variable bias voltage (reverse biased) to a Varactor diode, the capacitance is changed and the oscillating frequency is changed accordingly. The varactor diode working principles, if the reverse voltage of the diode is increased, then the size of the depletion region increases. Likewise, if the reverse voltage of the varactor diode is decreased, then the size of the depletion region decreases. Varactor diodes are widely used within the RF design arena. They provide a method of varying the capacitance within a circuit by the application of a control voltage. The advantage of Varactor diode is low noise. It generates less noise as compared to the other P-N junction diode. Thus, the power loss due to noise is low in Varactor diodes. The varactor diode is portable due to the small size and light weight. A Varactor diode modulator is the direct method of FM generation wherein the carrier frequency varied by the modulation signal (Vtune). A Varactor diode is a semiconductor diode whose junction capacitance varies linearly with applied voltage when the diode is reverse biased. The Varactor diode is arranged in reverse biased to offer Junction capacitance effect. The modulation voltage (Vtune) which is in series with the Varactor diode will vary the bias and hence the junction capacitance of the capacitance, resulting the oscillator frequency to change accordingly. The Varactor diode equivalent circuit (equivalent electrical model at high frequencies) for spice model includes the following elements: The package inductance Lp, is due to the lead inductance, wire bonds and other interconnect required to get to the diode device (Fig 2). The package capacitance, Cp, is due to the stray capacitance from the package and other features to the surrounding ground. In general, better quality diodes have minimal package effects and therefore Cp and Lp are small. The device resistance R(V) is the device resistance in the physical diode and will have some voltage dependence. If the tuning voltage range is limited, the voltage dependence of the resistance can be ignored. The resistance accounts of the finite Q of the diode and is due to the un-depleted region of the diode and contact resistance. The tuning capacitance, C(V), is the desired capacitance and it is strongly dependent upon the bias voltage. ; ; Assumption: The tuning voltage range of the Varactor is very narrow then we ignored the voltage dependence of the resistance, ( ) The reverse bias on the Varactor is V then KCL @ A6: KCL @ A9: ; load load ; ; Hint 1: ; ; k is Boltzmann's constant which is constant, q is the charge of an electron, T is temperature and it is not constant but humans exist in a fairly narrow range of temperatures around 300 0 K then 25mV to 26mV is a reasonable value for room temperature T V . "T" in T V stands for 'thermal' that is a function of (absolute) temperature. 1 ( ) Assumption: We operate d dt on the two sides of the above integral equation and get the following equation: We can summery our circuit Key differential equations (1): We can summery our circuit Key reduced differential equations (2): We can summery our circuit Key reduced differential equations (3): We define We choose 2 We can summery our circuit Key reduced differential equations (4): Case I: (85) We can summery our system fixed points: We implement the above equations with arbitrarily small increments of exponential form in our system's differential equations (First fixed point).
First equation: Second equation: At fixed points: Implementing our last result in (*) and we get the expression: We define for simplicity global parameter: Third equation: Fourth equation: At fixed points: We choose for simplicity We use the summation rule which is especially useful in probability theory. In practice A and B have to be switched on the right hand side of the equations if B > A then ( ln( ) ln( ) ln(1 ) By using Taylor series: Divide the two sides of the above equation by t e λ⋅ and assuming We can summery our equations with arbitrarily small increments of exponential form (1): Taking equation (D): We define for simplicity global parameters: Implement the last result in (B): (1 ) Implement the last result in (A): We can summery our equations with arbitrarily small increments of exponential form (2): Taking equation (F): We define for simplicity global parameters: Implement the last result in (E): We can summery our equations with arbitrarily small increments of exponential form (3): (H) Taking equation (I): Implement it in (H): Assumption: We divide the two sides of the above equation by 2 L i .
Assumption: n s a c t i o n s o n N e t w o r k s a n d C o m m u n i c a t i o n s ; V o l u m e 7 , N o . 3   We study the occurrence of any possible stability switching, resulting from the increase of the value of the time delayτ for the general characteristic equation ( , ) D λ τ [5] [6].     We assume ( , ) n P λ τ and ( , ) m Q λ τ cannot have common imaginary roots. That is for any real number ω : We define the following parameters for simplicity: 0 2 4 , , Π Π Π We use different parameters terminology from our last characteristics parameters definition: No roots bifurcation from ∞ . Indeed, in the limit: (c) The following expressions exist: Has at most a finite number of zeros. Indeed, this is a polynomial in ω (degree in 4 ω ).
(d) Each positive root In addition, since the coefficients in P and Q are real, we have (     When writing and inserting i λ ω = ⋅ into system's characteristic equation ω must satisfy the following equations. Where 2 | ( , ) | 0 Q i ω τ ⋅ ≠ in view of requirement (a) above, and ( , ) g h ∈  . Furthermore, it follows above sin( ) ω τ ⋅ and cos( ) ω τ ⋅ equations, that by squaring and adding the sides, ω must be a positive root of Where ; ; ;  ; ; When (x) can be any Free running VCO is based on an unstable transistor circuit parameter 1 2 , , , , , ,...
We choose our specific parameter as time delay x τ = .
2 0 2 4 6 0 0 0 Differentiating with respect toτ and we get Then we get the expression for ( , ) F ω τ circuit parameter values. We find those , ω τ values which fulfill ( , ) 0 F ω τ = . We ignore negative, complex, and imaginary values of ω for specific [0.001... 10] τ ∈ second. We plot the stability switch diagram based on different delay values of our free running VCO is based on an unstable transistor circuit.
Finally, we plot the stability switch diagram.

Free Running VCO based on an Unstable Transistor Applicable Integrated Circuits
In many RF and microwave systems, a frequency synthesizer is required. Free running VCO (based on unstable transistor) is an integral part of these systems. The frequency synthesizer creates the local oscillator signal that drives mixers, modulators, demodulators, and many other RF and microwave components. The key element of creating a synthesizer is using a phase-locked loop (PLL) frequency synthesizer. A simple PLL divided down the voltage controlled oscillator (Free running VCO) output frequency, compared this to a reference signal, and then tweaked the free running VCO voltage to weak its output frequency. The PLL and VCO have been two separate chips -a discrete solution. The free running VCO creates the actual output signal; the PLL monitors the output signals and tunes the free running VCO to lock it relative to a known reference signal. There are a number of strengths to the discrete solution: Each discrete chip can be designed to give its best performance, the typical distance between the PLL and the free running VCO reduces cross-coupling effects and minimizes unwanted spurious signals on the output. In case that one chip in the loop is damaged, fewer components need to be replaced. Discrete solutions which included VCOs, PLLs, DLLs, etc., dominated the synthesizer industrial applications. One major issue is that the discrete solution requires a lot of board space to hold the two chips and all their supporting components. Another major issue with the discrete solution is that traditional VCOs have a narrow output frequency range while the free running VCO is a very low cost and good solution to generate a WBFM signal. A typical VCO bandwidth is 50MHz to 500MHz; it's possible to go up around 2GHz but this requires an Op-amp based active filter. The major engineering challenge is to implement a system with a wider frequency range. To create a wider frequency range synthesizer, multiple PLLs, VCOs, supporting components, filtering, switches, and power supplies are needed. It increases the board space and cost of a design. Additional there is a huge amount of overhead work in qualifying, creating software for, and inventory controlling each device. The integrated solution meant the VCO architecture could change to create a wideband synthesizer from one component. The integrated PLL/VCO solution uses a different type of VCO architecture that builds on the traditional architecture. The integrated PLL/VCO effectively combines several traditional VCOs side-by-side to create a VCO with a remarkably wide bandwidth. The fact that the PLL and VCO are integrated onto one chip makes the multiband architecture possible. Every time the user wants to lock to a new frequency, the device initiates a VCO calibration process where the chip quickly sorts through the VCO bands and chooses the optimum one for the required output frequency. Once the VCO band has been selected, the PLL then locks the loop and keeps the output at the desired frequency. Important group of PLL/VCO chips has over 4GHz of bandwidth. We compare it to the discrete 100MHz to 300MHz bandwidth -and this frequency range is possible from a tiny chip relative to the previously required banks of PLLs, VCOs, filters, and switches. While this technology was a huge step forward in frequency range, board space, cost, and overhead, there were still drawbacks that stopped the integrated solution completely taking over from the discrete solution. In many applications, the most important performance specification (after frequency range) is phase noise. There is an additional drive for phase noise performance from the electric test and measurement industry. Whatever phase noise performance is used by the communications industry, the electric test and measurement instruments need better phase noise performance and they can measure the communication protocols. Many solutions were able to move from discrete to integrated -saving money in the process -the phase noise performance of the first generation PLL/VCOs simply was not good enough to replace many of the low phase noise requirement applications. As well as the phase noise performance, the frequency range was low compared to many of the applications that require a discrete PLL and VCO. The frequency range issue can be mitigated by frequency doubles and other multipliers, but there are high power consumption and add additional cost and board space to the solution. The new integrated PLL/VCOs have the following requirements: output frequencies greater than 4.4GHz, phase noise performance comparable with discrete solutions, an integrated PLL and VCO in a single and small package, and lower cost than discrete solutions. The second generation of integrated PLL/VCOs products is greater than 10GHz output frequency range, phase noise comparable to a discrete VCO, 5mm x 5mm packages, and at lower prices than a similar discrete PLL and VCO solution (which would have a much narrow frequency range). There is a phase noise performance which benefits of a discrete solution, plus all the other benefits of an integrated solution. The is a combination of the first generation of PLL/VCOs, PLL blocks and maximum phase frequency detector (PFD) frequencies around 32MHz and fractional-N divider resolutions of around 12 bits. This combination meant typical channel resolution is in the tens of kHz. The second generation of PLLs/VCO has maximum PFD frequencies greater than 100MHz and fractional-divider resolutions of 25 bits or even up to 49 bits. This had two main benefits -the higher PFD frequency allowed for lower PLL phase noise; and 25 bit or even more resolution allows exact frequency generation and Sub-Hz channel spacing. A very important aspect of the integrated PLL/VCO is spurious performance. One of the benefits of the discrete solution listed above is that the physical isolation between the two chips reduces cross coupling between the PLL and VCO and therefore reduces the power of unwanted spurious signals. When the PLL and VCO are integrated, it is inevitable that the spurious performance will degrade. We must keep this degradation very low and have surprisingly good spurious performance for a PLL/VCO. Other PLL/VCO parts need extra application work to improve the spurious levels for some high performance applications. The close proximity of the PLL and VCO circuits can result in unwanted coupling. To mitigate this, it is possible to use two chip solutions to physically separate the PLL and VCO circuits. This gives the discrete advantages of low spurious signals and the integrated advantages of a wide output frequency range. The following figure describes how to lock the microwave wideband synthesizer with integrated VCO and with an external Fractional-N PLL (typically 8GHz, 19 bit) to improve spurious performance. The R counter output Fractional-N PLL is calibrating /GND when synthesizer is holding lock (Fig. 3).

Fig. 3 Synthesizer with integrated VCO and an external Fractional-N PLL
PLL (phase lock loop) system is a control system that generates output signal which his phase is related to input signal phase. The PLL system includes the following main functional circuit, Variable frequency oscillator (Free running VCO), phase detector, and feedback loop. The frequency variable oscillator (Free running VCO) creates a periodic wave and the phase detector compares the signal phase to input periodic signal phase. It sets the oscillator frequency for keeping phase adaptation (Fig. 4). We lock in input and output signals phase, and then the input signal frequency and the output signal frequency are equal. The PLL unit tracks the input signal frequency or generates output signal which his frequency is multiplication of input signal frequency. We use PLL units for some typical applications: computer clock synchronization, demodulation, frequency synthesizer (Fig. 5). One important application is the process of comparing the input phase to the output phase of clock distribution.

Fig. 5 Clock distribution system with PLL
Additional applications are in demodulator unit which is tracking the modulation phase or modulation frequency. PLL unit can tracks on the carrier signal or changeable synchronization signal with frequency or time. When the PLL works as demodulator (detector), it is filter which is coherent detector. When PLL works as a carrier tracking system then it functions as narrow band filter which remove the noise from the signal. In one integrated package it includes a double balanced phase detector and highly linear VCO (Free running VCO). We set the frequency by external capacitor or resistor. The following block diagram describes the PLL signals and internal elements (Fig. 6).  to the input signal frequency then we are in lock state. Signal f e will keep the VCO output frequency to be equal to PLL input frequency and we are in lock state. The following flowchart describes the PLL frequency locking due to input signal frequency variation (Fig. 7).

Fig. 7 PLL frequency locking mechanism
We can detect the phase error due to frequency variation by knowing the "DC" loop gain of the system.
We consider that PLL's phase detector unit with transfer function ⋅ . The phase of free running VCO output is proportional to the integration of control voltage. The PLL free running frequency is established by PLL internal circuit and external capacitor and resistor. The following diagram describes the application of free running VCO as a FM demodulator system (Fig. 8).  Other applications to use free running VCO are CMOS/Bi-CMOS/Indium integrated circuit and DLL (Delay locked loop). A delay locked loop (DLL) is a digital circuit similar to a phase lock loop (PLL), with the main difference being the absence of an internal VCO, replaced by a delay line. A DLL can be used to change the phase of a lock signal, usually to enhance the clock rise-to-data output valid timing characteristics of integrated circuits. DLLs can also be used for clock recovery (CDR). A DLL can be seen as a negative-delay gate placed in the clock path of a digital circuit. The main component of a DLL is a delay chain composed of many delay gates connected output to input. The input of the chain is connected to the clock that is to be negatively delayed. A multiplexer is connected to each stage of the delay chain; the selector of this multiplexer is automatically updated by a control circuit to produce the negative delay effect. The output of the DLL is the resulting, negatively delayed clock signal. Indium phosphide Heterojunction Bipolar Transistors are used in RF and mixed signal circuits operating at frequencies from below 10GHz up to 0.2THz. At these high frequencies, digital circuit blocks are simulated carefully with techniques traditional to analog and millimeter wave circuit design. Transmission line techniques are used to interconnect subcircuits and additionally static frequency dividers circuits with HBT technology, applications in frequency agile digital radar and wireless communications systems. HBTs are excellent for implementing VCOs (free running VCO) due to their low transmission lines. SiGe HBT mm-wave VCOs have the advantage of large transistor voltage swings and low phase noise. Their power dissipation is excessive. CMOS VCOs at lower frequencies are popular due to their low power dissipation brought about by the significantly lower power supply voltage. A mm-wave CMOS VCOs suffer from inadequate output power levels, reduced tuning range and a very poor phase noise. There are applications which include SiGe BiCMOS PLL with integrated VCO RFICs. It enables miniature LO solutions. It includes an advanced fractional-N synthesizer and an ultra-low noise VCO while requiring a minimal number of external components. The PLL/Synthesizer can incorporates a cycle slip prevention (CSP) mode, which holds the PFD gain at maximum until the frequency difference is near zero reducing the time to arrive at the new frequency. PLL with integrated VCOs uniquely combine the attributes of low phase noise, wide frequency coverage, advanced features and ultra-small size, making them ideal for numerous small form factor applications.

Conclusion
We demonstrate the use of Varactor diode in a free running VCO based on an unstable transistor circuit system. The VCO is a key element to generate WBFM signals, such as chirp signals. Varactor diode is a simple tunable elements and it has inherently nonlinear behavior which disqualifies it for use in modern communication standards. The capacitance of a single Varactor diode can usually be expressed as where φ is the built-in potential of the diode, V is the applied voltage, n is the power law exponent of the diode capacitance, and K is the capacitance constant. The power law exponent can exhibit wide variation in different situations. It is value of 0.3 n ≈ for the implanted junction to 0.5 n ≈ for a uniformly doped junction to 1.5 n ≈ for a hyper-abrupt junction. The capacitance of Varactor diode may be varies by varying the reverse voltage applied to it thus, the Varactor also known as VVC (Voltage Variable Capacitor) diode. Their mode of operation depends on the capacitance that exists at the PN junction when it is reverse biased. As the Varactor diode reverse potential increases the width of the depletion region increases which in turn reduces the transition capacitance. When the Varactor diode reverse bias voltage decrease, the depletion layer narrows down. This decreases the dielectric thickness, which increases the capacitance. The variation of capacitance is maximum when the reverse voltage is equal to zero. It reduces in a nonlinear manner, as the value of reverse voltage is increased. In this diode the variation of capacitance are controlled by the method of doping in the depletion layer or the size and geometry of diode construction. The outcome of this article is an analysis of the stability, Free running VCO based on an unstable transistor circuit. Apply variable bias voltage to Varactor diode causes to capacitance change and the oscillating frequency is changed accordingly. The equivalent circuit includes three delay lines, the first delay line ( 1 τ ) represents the electromagnetic interference in the Varactor diode. The second and third delay lines ( 2 3 , τ τ ) represent the circuit microstrip lines parasitic effects before and after the matching circuit. We neglect the voltages on the three delay lines. We represent our system by DDEs which depend on variable parameters and delay parameters ( 1 2 3 , , τ τ τ ). We inspect the stability of any one of the equilibrium points of the Free running VCO which based on an unstable transistor circuit. The system of homogeneous equations leads to polynomial characteristic equation in the eigenvalues (under some assumptions). The stability switching is inspected for different values of τ parameter by using Beretta and Kuang stability criteria. There are many applications to use free running VCO, are CMOS/Bi-CMOS/Indium integrated circuit, PLLs, and DLL (Delay locked loop), our mathematical analysis help as to understand the operation of those application with integrated free running VCO.