1.
Ghosh A, Sinha A. Performance Analysis of FPGA Based MAC Unit using DBTNS Multiplier & TRNS Adder for Signal Processing Algorithm. EJAS [Internet]. 2018Nov.5 [cited 2020Oct.26];6(5):31. Available from: https://journals.scholarpublishing.org/index.php/AIVP/article/view/5394